Computer Architecture = ISA + Microarchitecture
- ISA (Instruction Set Architecture): the abstract model, e.g. CISC, RISC.
- Microarchitectures: the implementation of an ISA, e.g. Intel Skylake, AMD Zen 4, ARMv9-A, etc.
- CISC: Complex Instruction Set Computer, a large set of complex and specialized ones.
- RISC: Reduced Instruction Set Computer, simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, allows a computer's microprocessor to have fewer cycles per instruction (CPI) than CISC.
Examples: all x86 CPUs are CISC; ARM, RISC-V are RISC.
CISC. All Intel and AMD chips.
RISC. Arm Ltd. develops the architectures and licenses them to other companies. Can be found in most smartphones. Apple silicon is also based on ARM. More power efficient (comparing to x86).
RISC-V ISA is provided under open source licenses that do not require fees to use.
RISC-V International sets the specifications, and semiconductor designers like implement them as designs that can be slotted into system-on-chips for customers among other IP.
- SiFive is a fabless semiconductor company and provider of commercial RISC-V processor IP and silicon chips
- Alibaba open-sourced a bunch of RISC-V CPU designs under an Apache license.
RISC. Developed by OpenPOWER Foundation, originally developed by IBM.
Developed from MIPS.
- MIPS: RISC. In 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to RISC-V.
Intel Xeon is popular in data centers, besides that:
- Amazon AWS
- Graviton processors: using 64-bit Arm Neoverse cores https://aws.amazon.com/ec2/graviton/
- Google GCP:
- AMD EPYC processors.
- Microsoft Azure: Ampere Altra, "Cloud Native Server Processors", based on ARM.
- Alibaba: "We have taken a multiple ISA strategy. Today, our cloud computing provides the most number of ISAs. We have x86, ARM, RISC-V, and many more."
Arm forked the big core in the client segment into two series:
- Cortex-A7x: sustained efficient performance.
- Cortex-X series cores: focuse on peak bursty high performance.
- Cortex-X2: the first Armv9 based implementation. this core was specifically optimized for AArch64 only, as part of the ongoing effort to transition to 64-bit in the mobile space.
- Google Tensor has 2 Cortex-X1 cores.
SIMD: Single Instruction Multiple Data.
SIMD relates to vector data ops with a single instruction.
Arm Neon is an advanced SIMD architecture extension. Vastly improve use cases on mobile devices, such as multimedia encoding/decoding, user interface, 2D/3D graphics and gaming; accelerate signal processing algorithms and functions to speed up applications such as audio and video processing, voice and facial recognition, computer vision, and deep learning.